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| CAT28C16A 16 kb CMOS Parallel EEPROM Description The CAT28C16A is a fast, low power, 5V-only CMOS Parallel EEPROM organized as 2K x 8-bits. It requires a simple interface for in-system programming. On-chip address and data latches, self-timed write cycle with auto-clear and VCC power up/down write protection eliminate additional timing and protection hardware. DATA Polling signals the start and end of the self-timed write cycle. Additionally, the CAT28C16A features hardware write protection. The CAT28C16A is manufactured using ON Semiconductor's advanced CMOS floating gate technology. It is designed to endure 100,000 program/erase cycles and has a data retention of 100 years. The device is available in JEDEC approved 24-pin DIP and SOIC or 32-pin PLCC packages. Features http://onsemi.com SOIC-24 J, K, W, X SUFFIX CASE 751BK * Fast Read Access Times: 90 ns, 120 ns, 200 ns * Low Power CMOS Dissipation: * * * * * * * * - Active: 25 mA Max. - Standby: 100 mA Max. Simple Write Operation: - On-chip Address and Data Latches - Self-timed Write Cycle with Auto-clear Fast Write Cycle Time: 10 ms Max End of Write Detection: DATA Polling Hardware Write Protection CMOS and TTL Compatible I/O 100,000 Program/Erase Cycles 100 Year Data Retention Commercial, Industrial and Automotive Temperature Ranges PIN CONFIGURATION A7 NC NC NC VCC WE NC PDIP-24 L SUFFIX CASE 646AD PLCC-32 N, G SUFFIX CASE 776AK PIN FUNCTION Pin Name A0-A10 I/O0-I/O7 CE OE WE VCC VSS NC Function Address Inputs Data Inputs/Outputs Chip Enable Output Enable Write Enable 5 V Supply Ground No Connect DIP Package (L) SOIC Package (J, K, W, X) A7 A6 A5 A4 A3 A2 A1 A0 I/O0 I/O1 I/O2 VSS 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 VCC A8 A9 WE OE A10 CE I/O7 I/O6 I/O5 I/O4 I/O3 A6 A5 A4 A3 A2 A1 A0 NC I/O0 PLCC Package (N, G) ORDERING INFORMATION A8 A9 NC NC OE A10 CE I/O7 I/O6 See detailed ordering and shipping information in the package dimensions section on page 10 of this data sheet. 4 3 2 1 32 31 30 5 29 6 28 7 27 8 26 9 25 TOP VIEW 10 24 11 23 12 22 13 21 14 15 16 17 18 19 20 I/O1 I/O2 VSS NC I/O3 I/O4 I/O5 (c) Semiconductor Components Industries, LLC, 2009 October, 2009 - Rev. 6 1 Publication Order Number: CAT28C16A/D CAT28C16A A4-A10 ADDR. BUFFER & LATCHES INADVERTENT WRITE PROTECTION ROW DECODER 2,048 x 8 EEPROM ARRAY VCC HIGH VOLTAGE GENERATOR CE OE WE CONTROL LOGIC I/O BUFFERS DATA POLLING I/O0-I/O7 TIMER ADDR. BUFFER & LATCHES A0-A3 COLUMN DECODER Figure 1. Block Diagram Table 1. MODE SELECTION Mode Read Byte Write (WE Controlled) Byte Write (CE Controlled) Standby, and Write Inhibit Read and Write Inhibit H X CE L L L X H WE H OE L H H X H I/O DOUT DIN DIN High-Z High-Z Power ACTIVE ACTIVE ACTIVE STANDBY ACTIVE Table 2. CAPACITANCE (TA = 25C, f = 1.0 MHz, VCC = 5 V) Symbol CI/O (Note 1) CIN (Note 1) Test Input/Output Capacitance Input Capacitance Max 10 6 Conditions VI/O = 0 V VIN = 0 V Units pF pF 1. This parameter is tested initially and after a design or process change that affects the parameter. Table 3. ABSOLUTE MAXIMUM RATINGS Parameters Temperature Under Bias Storage Temperature Voltage on Any Pin with Respect to Ground (Note 2) VCC with Respect to Ground Package Power Dissipation Capability (TA = 25C) Lead Soldering Temperature (10 secs) Output Short Circuit Current (Note 3) Ratings -55 to +125 -65 to +150 -2.0 V to +VCC + 2.0 V -2.0 to +7.0 1.0 300 100 Units C C V V W C mA Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. 2. The minimum DC input voltage is -0.5 V. During transitions, inputs may undershoot to -2.0 V for periods of less than 20 ns. Maximum DC voltage on output pins is VCC + 0.5 V, which may overshoot to VCC + 2.0 V for periods of less than 20 ns. 3. Output shorted for no more than one second. No more than one output shorted at a time. http://onsemi.com 2 CAT28C16A Table 4. RELIABILITY CHARACTERISTICS (Note 4) Symbol NEND (Note 5) TDR (Notes 5) VZAP ILTH (Note 6) Endurance Data Retention ESD Susceptibility Latch-Up Parameter Min 100,000 100 2,000 100 Max Units Cycles/Byte Years V mA 4. This parameter is tested initially and after a design or process change that affects the parameter. 5. For the CAT28C16A-20, the minimum endurance is 10,000 cycles and the minimum data retention is 10 years. 6. Latch-up protection is provided for stresses up to 100 mA on address and data pins from -1 V to VCC + 1 V. Table 5. D.C. OPERATING CHARACTERISTICS (VCC = 5 V 10%, unless otherwise specified.) Limits Symbol ICC ICCC (Note 7) ISB ISBC (Note 8) ILI ILO VIH (Note 8) VIL (Note 7) VOH VOL VWI Parameter VCC Current (Operating, TTL) VCC Current (Operating, CMOS) VCC Current (Standby, TTL) VCC Current (Standby, CMOS) Input Leakage Current Output Leakage Current High Level Input Voltage Low Level Input Voltage High Level Output Voltage Low Level Output Voltage Write Inhibit Voltage IOH = -400 mA IOL = 2.1 mA 3.0 Test Conditions CE = OE = VIL, f = 1/tRC min, All I/O's Open CE = OE = VILC, f = 1/tRC min, All I/O's Open CE = VIH, All I/O's Open CE = VIHC, All I/O's Open VIN = GND to VCC VOUT = GND to VCC, CE = VIH -10 -10 2 -0.3 2.4 0.4 Min Typ Max 35 25 1 100 10 10 VCC + 0.3 0.8 Units mA mA mA mA mA mA V V V V V 7. VILC = -0.3 V to +0.3 V 8. VIHC = VCC - 0.3 V to VCC + 0.3 V Table 6. A.C. CHARACTERISTICS, READ CYCLE (VCC = 5 V 10%, unless otherwise specified.) 28C16A-90 Symbol tRC tCE tAA tOE tLZ (Note 9) tOLZ (Note 9) tHZ (Notes 9, 10) tOHZ (Notes 9, 10) tOH (Note 9) Parameter Read Cycle Time CE Access Time Address Access Time OE Access Time CE Low to Active Output OE Low to Active Output CE High to High-Z Output OE High to High-Z Output Output Hold from Address Change 0 0 0 50 50 0 Min 90 90 90 50 0 0 50 50 0 Max 28C16A-12 Min 120 120 120 60 0 0 55 55 Max 28C16A-20 Min 200 200 200 80 Max Units ns ns ns ns ns ns ns ns ns 9. This parameter is tested initially and after a design or process change that affects the parameter. 10. Output floating (High-Z) is defined as the state when the external data line is no longer driven by the output buffer. http://onsemi.com 3 CAT28C16A 2.4 V INPUT PULSE LEVELS 0.45 V 2.0 V 0.8 V REFERENCE POINTS Figure 2. A.C. Testing Input/Output Waveform (Note 11) 11. Input rise and fall times (10% and 90%) < 10 ns. 1.3V 1N914 3.3K DEVICE UNDER TEST OUT CL = 100 pF CL INCLUDES JIG CAPACITANCE Figure 3. A.C. Testing Load Circuit (example) Table 7. A.C. CHARACTERISTICS, WRITE CYCLE (VCC = 5 V 10%, unless otherwise specified.) 28C16A-90 Symbol tWC tAS tAH tCS tCH tCW (Note 12) tOES tOEH tWP (Note 12) tDS tDH tDL tINIT (Note 13) Parameter Write Cycle Time Address Setup Time Address Hold Time CE Setup Time CE Hold Time CE Pulse Time OE Setup Time OE Hold Time WE Pulse Width Data Setup Time Data Hold Time Data Latch Time Write Inhibit Period After Power-up 0 100 0 0 110 0 0 110 60 0 5 0.05 10 100 Min Max 5 0 100 0 0 110 0 0 110 60 0 5 0.05 10 100 28C16A-12 Min Max 5 10 100 0 0 150 15 15 150 50 10 50 5 20 28C16A-20 Min Max 10 Units ms ns ns ns ns ns ns ns ns ns ns ns ms 12. A write pulse of less than 20 ns duration will not initiate a write cycle. 13. This parameter is tested initially and after a design or process change that affects the parameter. http://onsemi.com 4 CAT28C16A DEVICE OPERATION Read Data stored in the CAT28C16A is transferred to the data bus when WE is held high, and both OE and CE are held low. The data bus is set to a high impedance state when either CE or OE goes high. This 2-line control architecture can be used to eliminate bus contention in a system environment. tRC ADDRESS tCE CE OE tOE WE VIH tLZ tOLZ tAA tOH DATA VALID tOHZ tHZ DATA VALID DATA OUT HIGH-Z Figure 4. Read Cycle tWC ADDRESS tAS tCS CE tAH tCH OE tOES WE tDL DATA OUT HIGH-Z tWP tOEH DATA IN DATA VALID tDS tDH Figure 5. Byte Write Cycle [WE Controlled] Byte Write A write cycle is executed when both CE and WE are low, and OE is high. Write cycles can be initiated using either WE or CE, with the address input being latched on the falling edge of WE or CE, whichever occurs last. Data, conversely, is latched on the rising edge of WE or CE, whichever occurs first. Once initiated, a byte write cycle automatically erases the addressed byte and the new data is written within 10 ms. http://onsemi.com 5 CAT28C16A DATA Polling DATA polling is provided to indicate the completion of a byte write cycle. Once a byte write cycle is initiated, attempting to read the last byte written will output the complement of that data on I/O7 (I/O0-I/O6 are indeterminate) until the programming cycle is complete. Upon completion of the self-timed byte write cycle, all I/O's will output true data during a read cycle. tWC ADDRESS tAS tAH tCW CE tOEH OE tCS WE HIGH-Z DATA OUT tOES tCH tDL DATA IN DATA VALID tDS tDH Figure 6. Byte Write Cycle [CE Controlled] ADDRESS CE WE tOEH OE tWC I/O7 DIN = X DOUT = X DOUT = X tOE tOES Figure 7. DATA Polling Hardware Data Protection The following is a list of hardware data protection features that are incorporated into the CAT28C16A. 1. VCC sense provides for write protection when VCC falls below 3.0 V min. 2. A power on delay mechanism, tINIT (see AC characteristics), provides a 5 to 20 ms delay before a write sequence, after VCC has reached 3.0 V min. 3. Write inhibit is activated by holding any one of OE low, CE high or WE high. 4. Noise pulses of less than 20 ns on the WE or CE inputs will not result in a write cycle. http://onsemi.com 6 CAT28C16A PACKAGE DIMENSIONS PLCC 32 CASE 776AK-01 ISSUE O PIN#1 IDENTIFICATION E1 E E2 D1 D TOP VIEW A3 END VIEW A2 SYMBOL b1 A2 A3 b b1 b D2 SIDE VIEW Notes: (1) All dimensions are in millimeters. (2) Complies with JEDEC MS-016. e D D1 D2 E E1 E2 e MIN 0.38 2.54 0.33 0.66 12.32 11.36 9.56 14.86 13.90 12.10 NOM MAX 2.80 0.54 0.82 12.57 11.50 11.32 15.11 14.04 13.86 1.27 BSC http://onsemi.com 7 CAT28C16A PACKAGE DIMENSIONS SOIC-24, 300 mils CASE 751BK-01 ISSUE O SYMBOL A A1 A2 b E1 E c D E E1 e h b PIN#1 IDENTIFICATION TOP VIEW e L 0.25 0.40 MIN 2.35 0.10 2.05 0.31 0.20 15.20 10.11 7.34 NOM MAX 2.65 0.30 2.55 0.51 0.33 15.40 10.51 7.60 1.27 BSC 0.75 1.27 1 0 5 8 15 D h h q1 A A2 q q1 END VIEW A1 SIDE VIEW L c Notes: (1) All dimensions are in millimeters. Angles in degrees. (2) Complies with JEDEC MS-013. http://onsemi.com 8 CAT28C16A PACKAGE DIMENSIONS PDIP-24, 600 mils CASE 646AD-01 ISSUE A SYMBOL A A1 A2 E1 E b b1 c D D E E1 e TOP VIEW eB L 15.24 2.93 0.39 3.18 0.36 0.77 0.21 31.50 15.24 12.32 2.54 BSC 17.78 5.08 4.95 0.55 1.77 0.38 32.25 15.87 14.73 MIN NOM MAX 6.35 A2 A c A1 b1 e b L eB SIDE VIEW END VIEW Notes: (1) All dimensions are in millimeters. (2) Complies with JEDEC MS-011. http://onsemi.com 9 CAT28C16A Example of Ordering Information Prefix CAT Device # 28C16A Suffix N I - 20 T Company ID (Optional) Product Number 28C16A Temperature Range Blank = Commercial (0C to +70C) I = Industrial (-40C to +85C) A = Automotive (-40C to +105C) Speed -90: 90 ns -12: 120 ns -20: 200 ns Tape & Reel (Note 15) T: Tape & Reel Package N: PLCC J: SOIC (JEDEC) K: SOIC (EIAJ) L: PDIP (Lead Free, Halogen Free) G: PLCC (Lead Free, Halogen Free) W: SOIC (JEDEC) (Lead Free, Halogen Free) X: SOIC (EIAJ) (Lead Free, Halogen Free) 14. The device used in the above example is a CAT28C16ANI-20T (PLCC, Industrial Temperature, 200 ns Access Time, Tape & Reel). 15. For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. "Typical" parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. PUBLICATION ORDERING INFORMATION LITERATURE FULFILLMENT: Literature Distribution Center for ON Semiconductor P.O. Box 5163, Denver, Colorado 80217 USA Phone: 303-675-2175 or 800-344-3860 Toll Free USA/Canada Fax: 303-675-2176 or 800-344-3867 Toll Free USA/Canada Email: orderlit@onsemi.com N. American Technical Support: 800-282-9855 Toll Free USA/Canada Europe, Middle East and Africa Technical Support: Phone: 421 33 790 2910 Japan Customer Focus Center Phone: 81-3-5773-3850 ON Semiconductor Website: www.onsemi.com Order Literature: http://www.onsemi.com/orderlit For additional information, please contact your local Sales Representative http://onsemi.com 10 CAT28C16A/D |
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